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HD-15530
March 1997
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15530 is a high performance CMOS device intended to service the requirements of MlL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate completely independent of each other, except for the Master Reset functions. This circuit meets many of the requirements of MIL-STD1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. This integrated circuit is fully guaranteed to support the 1MHz data rate of MlL-STD-1553 over both temperature and voltage. It interfaces with CMOS, TTL or N channel support circuitry, and uses a standard 5V supply. The HD-15530 can also be used in many party line digital data communications applications, such as an environmental control system driven from a single twisted pair cable of fiber optic cable throughout the building.
Features
* Support of MlL-STD-1553 * Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s * Sync Identification and Lock-In * Clock Recovery * Manchester II Encode, Decode * Separate Encode and Decode * Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE CERDIP TEMP. RANGE -40oC to +85oC -55oC to +125oC SMD# CLCC -40oC to +85oC -55oC to +125oC -40oC to +85oC 1.25 MEGABIT/s HD1-15530-9 HD1-15530-8 7802901JA HD4-15530-9 HD4-15530-8 78029013A HD3-15530-9 E24.6 J28.A PKG. NO. F24.6
SMD# PDIP
Pinouts
HD-15530 (CERDIP, PDIP) TOP VIEW
VALID WORD 1 ENCODER SHIFT CLK 2 TAKE DATA 3 SERIAL DATA OUT 4 DECODER CLK 5 BIPOLAR ZERO IN 6 BIPOLAR ONE IN 7 UNIPOLAR DATA IN 8 DECODER SHIFT CLK 9 COMMAND/ DATA SYNC 10 DECODER RESET 11 GND 12 24 VCC 23 ENCODER CLK 22 SEND CLK IN 21 SEND DATA 20 SYNC SELECT 19 ENCODER ENABLE 18 SERIAL DATA IN 17 BIPOLAR ONE OUT 16 OUTPUT INHIBIT BIPOLAR 15 ZERO OUT 14 / 6 OUT 13 MASTER RESET NC BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLK 7 8 9 10 11 12 COMMAND/ DATA SYNC 13 DECODER RESET 14 GND 15 MASTER RESET 16 17 BIPOLAR ZERO OUT 18 OUTPUT INHIBIT 23 22 21 20 19 NC SYNC SELECT ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT DECODER CLK NC 5 6 SERIAL DATA OUT
HD-15530 (CLCC) TOP VIEW
TAKE DATA ENCODER SHIFT CLK ENCODER CLK SEND CLK IN 27 26 25 24 SEND DATA NC
VALID WORD 1
4
3
2
/ 6 OUT
VCC 28
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2960.1
5-142
HD-15530 Block Diagrams
ENCODER
12 13 22 14 GND MASTER RESET SEND CLK IN VCC OUTPUT INHIBIT 24 UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ZERO IN 8 7 6 TRANSITION FINDER CHARACTER IDENTIFIER
DECODER
3 TAKE DATA 10 4 5 BIT RATE CLK COMMAND/ DATA SYNC SERIAL DATA OUT
/ 6 OUT /6
ENCODER CLK BIT COUNTER
/2
17 CHARACTER FORMER 15
16 BIPOLAR ONE OUT BIPOLAR ZERO OUT
23
DECODER CLK 18 19 20 SYNC SELECT MASTER RESET
SYNCHRONIZER
PARITY 1 VALID CHECK WORD 9 DECODER SHIFT CLK
13 DECODER RESET 11 BIT COUNTER
21
2
SEND DATA
SERIAL DATA IN
ENCODER ENABLE ENCODER SHIFT CLK
Pin Description
PIN NUMBER 1 2 3 4 5 TYPE O O O O I NAME VALID WORD ENCODER SHIFT CLOCK TAKE DATA SERIAL DATA OUT DECODER CLOCK SECTION Decoder Encoder Decoder Decoder Decoder DESCRIPTION Output high indicates receipt of a valid word, (valid parity and no Manchester errors). Output for shifting data into the Encoder. The Encoder samples SDI on the low-to-high transition of Encoder Shift Clock. Output is high during receipt of data after identification of a sync pulse and two valid Manchester data bits. Delivers received data in correct NRZ format. Input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the decoder, input a frequency equal to 12X the data rate. A high input should be applied when the bus is in its negative state. This pin must be held high when the Unipolar input is used. A high input should be applied when the bus is in its positive state. This pin must be held low when the Unipolar input is used. With pin 6 high and pin 7 low, this pin enters unipolar data into the transition finder circuit. If not used this input must be held low. Output which delivers a frequency (DECODER CLOCK / 12), synchronized by the recovered serial data stream. Output of a high from this pin occurs during output of decoded data which was preceded by a Command (or Status) synchronizing character. A low output indicates a Data synchronizing character. A high input to this pin during a rising edge of DECODER SHIFT CLOCK resets the decoder bit counting logic to a condition ready for a new word. Ground Supply pin. A high on this pin clears 2:1 counters in both Encoder and Decoder, and resets the / 6 circuit. Output from 6:1 divider which is driven by the ENCODER CLOCK. An active low output designed to drive the zero or negative sense of a bipolar line driver. A low on this pin forces pin 15 and 17 high, the inactive states. An active low output designed to drive the one or positive sense of a bipolar line driver.
6 7 8 9 10
I I I O O
BIPOLAR ZERO IN BIPOLAR ONE IN UNLPOLAR DATA IN DECODER SHIFT CLOCK COMMAND SYNC
Decoder Decoder Decoder Decoder Decoder
11 12 13 14 15 16 17
I I I O O I O
DECODER RESET GROUND MASTER RESET
Decoder Both Both Encoder Encoder Encoder Encoder
/ 6 OUT
BIPOLAR ZERO OUT OUTPUT INHIBIT BIPOLAR ONE OUT
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HD-15530 Pin Description
PIN NUMBER 18 19 20 21 22 23 24 I = Input TYPE I I I O I I I (Continued)
NAME SERIAL DATA IN ENCODER ENABLE SYNC SELECT SEND DATA SEND CLOCK IN ENCODER CLOCK VCC
SECTION Encoder Encoder Encoder Encoder Encoder Encoder Both
DESCRIPTION Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. A high on this pin initiates the encode cycle. (Subject to the preceeding cycle being complete.) Actuates a Command sync for an input high and Data sync for an input low. An active high output which enables the external source of serial data. Clock input at a frequency equal to the data rate X2, usually driven by / 6 output. Input to the 6:1 divider, a frequency equal to the data rate X12 is usually input here. VCC is the +5V power supply pin. A 0.1F decoupling capacitor from VCC (pin 24) to GROUND (pin 12) is recommended.
O = Output
Encoder Operation
The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SEND CLOCK by dividing the DECODER CLOCK. The Encoder's cycle begins when ENCODER ENABLE is high during a falling edge of ENCODER SHIFT CLOCK 1 . This cycle lasts for one word length or twenty ENCODER SHIFT CLOCK periods. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high SYNC SELECT input actuates a command sync or a low will produce a data sync for the word 2 . When the Encoder is ready to accept data, the SEND DATA output will go high and remain high for sixteen ENCODER SHIFT CLOCK periods 3 . During these sixteen periods the data should be clocked into the SERIAL DATA input with every high-to-low transition of the ENCODER SHIFT CLOCK so it can be sampled on the lowto-high transition 3 - 4 . After the sync and Manchester II coded data are transmitted through the BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder adds on an additional bit which is the parity for that word 5 . If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time 5 as shown to prevent a consecutive word from being encoded. At any time a low on OUTPUT INHIBIT input will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To abort the Encoder transmission a positive pulse must be applied at MASTER RESET. Anytime after or during this pulse, a low-to-high transition on SEND CLOCK clears the internal counters and initializes the Encoder for a new word.
TIMING SEND CLK ENCODER SHIFT CLK ENCODER ENABLE SYNC SELECT SEND DATA SERIAL DATA IN BIPOLAR ONE OUT BIPOLAR ZERO OUT 12
0
1
2
3
4
5
6
7
15
16
17
18
19
DON'T CARE VALID DON'T CARE
15
1ST HALF 2ND HALF
14 15 15 14 14
13 13 13
12 12 12
11 11 11
10
3 3 3
2 2 2
1 1 1
0 0 0 P P
SYNC
SYNC
3
4
5
FIGURE 1.
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HD-15530 Decoder Operation
The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DECODER CLOCK input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BIPOLAR ONE and BIPOLAR ZERO inputs will accept data from a comparator sensed transformer coupled bus as specified in Military Spec 1553. The UNIPOLAR DATA input can only accept non-inverted Manchester II coded data. (e.g. from BIPOLAR ONE OUT of an Encoder through an inverter to Unipolar Data Input). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized 1 , the type of sync is indicated on COMMAND/DATA SYNC output. If the sync character was a command sync, this output will go high 2 and remain high for sixteen DECODER SHIFT CLOCK periods 3 , otherwise it will remain low. The TAKE DATA output will go high and remain high 2 - 3 while the Decoder is transmitting the decoded data through SERIAL DATA OUT. The decoded data available at SERIAL DATA OUT is in NRZ format. The DECODER SHIFT CLOCK is provided so that the decoded bits can be shifted into an external register on every low-tohigh transition of this clock 2 - 3 . Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. After all sixteen decoded bits have been transmitted 3 the data is checked for odd parity. A high on VALID WORD output 4 indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately 20 DECODER SHIFT CLOCK periods after it goes high if not reset low sooner by a valid sync and two valid Manchester bits as shown 1 . At any time in the above sequence a high input on DECODER RESET during a low-to-high transition of DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.
TIMING DECODER SHIFT CLK BIPOLAR ONE IN BIPOLAR ZERO IN TAKE DATA
0
1
2
3
4
5
6
7
8
16
17
18
19
1ST HALF 2ND HALF
15 15
14 14
13 13
12 12
11 11
10 10
2 2
1 1
0 0
P P
SYNC
SYNC
COMMAND/ DATA SYNC
SERIAL DATA OUT VALID WORD
UNDEFINED (FROM PREVIOUS RECEPTION)
15
14
13
12
4
3
2
1
0
1 2
3
4
FIGURE 2.
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HD-15530 How to Make Our MTU Look Like a Manchester Encoded UART
VALID WORD DECODER ENCODER CLK 1 BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN COMMAND SYNC DECODER RESET 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BIPOLAR ONE OUT INHIBIT OUTPUT BIPOLAR ZERO OUT MASTER RESET ENCODER ENABLE VCC SYNC SELECT
A
B
CK H
A
B
CK
74LS164
74LS164
OH SH/LD CK SI OH SH/LD CK 74165 74165
PARALLEL OUT
PARALLEL IN
FIGURE 3.
Typical Timing Diagrams for a Manchester Encoded UART
VALID ENCODER ENABLE SYNC SELECT PARALLEL IN BIPOLAR ONE OUT BIPOLAR ZERO OUT SYNC MSB LSB P P PARITY VALID
FIGURE 4. ENCODER TIMING
SYNC BIPOLAR ONE IN BIPOLAR ZERO IN COMMAND SYNC PARALLEL OUT VALID WORD VALID FROM PREVIOUS RECEPTION
MSB
LSB
PARITY P P
VALID
FIGURE 5. DECODER TIMING
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HD-15530 MIL-STD-1553
The 1553 standard defines a time division multiplexed data bus for application within aircraft. The bus is defined to be bipolar, and encoded in a Manchester II format, so no DC component appears on the bus. This allows transformer coupling and excellent isolation among systems and their environment. The HD-15530 supports the full bipolar configuration, assuming a bus driver configuration similar to that in Figure 1. Bipolar inputs from the bus, like Figure 2, are also accommodated. The signaling format in MlL-STD-1553 is specified on the assumption that the network of 32 or fewer terminals are controlled by a central control unit by means of Command
BUS + "1" REF "0" REF + "0" BUS "0" "1"
Words. Terminals respond with Status Words. Each word is preceded by a synchronizing pulse, and followed by parity bit, occupying a total of 20s. The word formats are shown in Figure 4. The special abbreviations are as follows: P R/T ME TF Parity, which is defined to be odd, taken across all 17 bits. Receive on logical zero, transmit on ONE. Message Error if logical 1. Terminal Flat, if set, calls for controller to request self-test data.
The paragraphs above are intended only to suggest the content of MlL-STD-1553, and do not completely describe its bus requirements, timing or protocols.
"1"
FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER
FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER
COMMAND SYNC
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
COMMAND WORD (FROM CONTROLLER TO TERMINAL) 5 DATA SYNC SYNC TERMINAL ADDRESS R/T BIT PERIOD BIT PERIOD BIT PERIOD 1 5 SUB ADDRESS /MODE 5 DATA WORD COUNT 1 P
DATA WORD (SENT EITHER DIRECTION) 16 1 P
LOGICAL ONE DATA
SYNC
CONTROL WORD
STATUS WORD (FROM TERMINAL TO CONTROLLER) 5 LOGICAL ZERO DATA SYNC TERMINAL ADDRESS ME 1 9 CODE FOR FAILURE MODES 1 1
TF P
FIGURE 8. MIL-STD-1553 CHARACTER FORMATS
FIGURE 9. MIL-STD-1553 WORD FORMATS
NOTE: This page is a summary of MIL-STD-1553 and is not intended to describe the operation of the HD-15530.
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HD-15530
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 55 12 CLCC Package . . . . . . . . . . . . . . . . . . 65 14 Plastic DIP Package . . . . . . . . . . . . . . 60 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range (TA) HD-15530-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC HD-15530-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Encoder/Decoder Clock Rise Time . . . . . . . . . . . . . . . . . . .8ns Max Encoder/Decoder Clock Fall Time . . . . . . . . . . . . . . . . . . . .8ns Max Sync Transition Span (TD2) . . . . . . . . . . . . . . . 18 TDC Typ (Note 1) Short Data Transition Span (TD4) . . . . . . . . . . . 6 TDC Typ (Note 1) Long Data Transition Span (TD5) . . . . . . . . . . . 12 TDC Typ (Note 1)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5V 10%, TA = -40oC to +85oC (HD-15530-9) TA = -55oC to +125oC (HD-15530-8) LIMITS
PARAMETER Input LOW Voltage Input HIGH Voltage Input LOW Clock Voltage Input HIGH Clock Voltage Output LOW Voltage Output HIGH Voltage Input Leakage Current Standby Supply Current Operating Power Supply Current Function Test NOTES:
SYMBOL VIL VlH VILC VIHC VOL VOH II ICCSB ICCOP FT
MIN 0.7 VCC VCC -0.5 2.4 -1.0 -
MAX 0.2 VCC GND +0.5 0.4 +1.0 2 10 -
TEST CONDITIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V IOL = 1.8mA (Note 2), VCC = 4.5V IOH = -3mA (Note 2), VCC = 4.5V VI = GND or VCC, VCC = 5.5V VIN = VCC = 5.5V Output Open VCC = 5.5V, VIN = VCC, f =15MHz, Outputs Open (Note 3)
UNITS V V V V V V A mA mA -
1. TDC = Decoder clock period = 1/FDC 2. Interchanging of force and sense conditions is permitted. 3. Tested as follows: = f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH 1.5V and VOL 1.5V.
Capacitance
SYMBOL CIN CO
TA = +25oC; Frequency = 1MHz PARAMETER Input Capacitance Output Capacitance TYPICAL 15 15 UNITS pF pF CONDITIONS All measurements are referenced to device GND
5-148
HD-15530
AC Electrical Specifications
VCC = 5V 10%, TA = -40oC to +85oC (HD-15530-9) TA = -55oC to +125oC (HD-15530-8) (NOTE 2) TEST CONDITIONS LIMITS MIN MAX UNITS
PARAMETER ENCODER TIMING Encoder Clock Frequency Send Clock Frequency Encoder Data Rate Master Reset Pulse Width Shift Clock Delay Serial Data Setup Serial Data Hold Enable Setup Enable Pulse Width Sync Setup Sync Pulse Width Send Data Delay Bipolar Output Delay Enable Hold Sync Hold DECODER TIMING Decoder Clock Frequency Decoder Data Rate Decoder Reset Pulse Width Decoder Reset Setup Time Decoder Reset Hold Time Master Reset Pulse Bipolar Data Pulse Width One Zero Overlap Sync Delay (ON) Take Data Delay (ON) Serial Data Out Delay Sync Delay (OFF) Take Data Delay (OFF) Valid Word Delay NOTES:
SYMBOL
FEC FESC FED TMR TE1 TE2 TE3 TE4 TE5 TE6 TE7 TE8 TE9 TE10 TE11
VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF
150 75 75 90 100 55 150 0 10 95
15 2.5 1.25 125 50 130 -
MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns
FDC FDD TDR TDRS TDRH TMR TD1 TD3 TD6 TD7 TD8 TD9 TD10 TD11
VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF
150 75 10 150 TDC + 10 (Note 1) -20 0 0 0 0
15 1.25 TDC - 10 (Note 1) 110 110 80 110 110 110
MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns
1. TDC = Decoder clock period = 1/FDC 2. AC Testing as follows: Input levels: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference levels: 1.5V; Output load: CL = 50pF.
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HD-15530 Timing Waveforms
SEND CLOCK TE1 ENCODER SHIFT CLOCK TE2 SERIAL DATA IN VALID TE3 VALID
SEND CLOCK TE1 ENCODER SHIFT CLOCK TE4 ENCODER ENABLE TE5 SYNC SELECT TE6 VALID TE7
ENCODER SHIFT CLOCK TE8 SEND DATA
SEND CLOCK BIPOLAR ONE OUT OR BIPOLAR ZERO OUT TE9
FIGURE 10. ENCODER TIMING
DECODER SHIFT CLOCK TD6 COMMAND/DATA SYNC TAKE DATA TD7
DECODER SHIFT CLOCK TD8 SERIAL DATA OUT DATA BIT
DECODER SHIFT CLOCK TD9 COMMAND/DATA SYNC TD10 TAKE DATA VALID WORD TD11
DECODER SHIFT CLOCK TDRS DECODER RESET TDR TDRH
FIGURE 11. DECODER TIMING
5-150
HD-15530 Timing Waveforms
(Continued)
NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS.
BIT PERIOD BIT PERIOD BIT PERIOD
BIPOLAR ONE IN BIPOLAR ZERO IN TD1 TD2
TD3 TD1
COMMAND SYNC
TD2
TD3
BIPOLAR ONE IN BIPOLAR ZERO IN TD1 TD2
DATA SYNC
TD1 TD3
TD3
TD2
TD1 BIPOLAR ONE IN TD3 BIPOLAR ZERO IN TD4 ONE TD3 TD1 TD5
TD1 TD3 TD3 TD1 TD5 ZERO ONE TD4 TD3
NOTE: BIPOLAR ONE IN = 0; BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS. UNIPOLAR IN TD2
COMMAND SYNC
TD2
UNIPOLAR IN
TD2
DATA SYNC
TD2 TD5 TD4 ONE
UNIPOLAR IN
TD4 ONE
TD5 ZERO
TD4 ONE
FIGURE 12. DECODER TIMING
Test Load Circuit
DUT CL9 (NOTE)
AC Testing Input, Output Waveform
INPUT VIH 50% VIL 50% VOL OUTPUT VOH
NOTE: Includes stray and jig capacitance.
AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt.
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HD-15530 Burn-In Circuits
HD1-15530 CERDIP
VCC C1 GND A A A A F0 R1 1 2 3 4 5 6 R1 GND A A GND GND R1 7 8 9 10 11 12 R1 R1 24 23 22 21 20 19 18 17 16 15 14 13 R1 R1 GND GND R1 R1 R1 GND VCC GND R1 VCC A VCC A R1 VCC F0
R1
HD4-15530 CLCC
VCC GND GND GND GND C1
R2 4 F0 NC NC 5 6 7 8 9 GND GND R2 11 12 R2 R2 R2 13 10 3
R2 2
R2 1
R2 28 27
F0
26 25 24 23 22 21 20 19
R2 GND NC NC GND VCC GND
14
15
16
17
18 VCC
GND GND GND GND
NOTES: 1. VCC = 5.5V 0.5V 2. VIH = 4.5V 10% 3. VIL = -0.2V +0.4V 4. R1 = 47K 5% 5. R2 = 1.8K 5% 6. F0 = 100KHz 10% 7. C1 = 0.01F Min.
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HD-15530 Die Characteristics
DIE DIMENSIONS: 155 x 195 x 19mils METALLIZATION: Type: Si-Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.8 x 105 A/cm2
Metallization Mask Layout
HD-15530
ENCODER SHIFT CLK TAKE DATA SEND CLK IN SERIAL DATA OUT VCC VALID WORD
ENCODER CLK
SEND DATA
DECODER CLK
SYNC SELECT
BIPOLAR ZERO IN BIPOLAR ONE IN
ENCODER ENABLE
SERIAL DATA IN UNIPOLAR DATA IN BIPOLAR ONE OUT
DECODER SHIFT CLK OUTPUT INHIBIT
COMMAND/DATA SYNC DECODER RESET GND MASTER RESET
BIPOLAR ZERO OUT
/ 6 OUT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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